1. Field of the Invention
The present invention relates to a booster circuit and a semiconductor integrated circuit device incorporating the booster circuit.
2. Description of Related Art
Along with the recent trend of using low-voltage power, voltage necessary for drive is now often generated by booster circuits. For example, what is sometimes used in a power circuit of a TFT (Thin Film Transistor) driver IC (Integrated Circuit) that drives liquid crystal displays is a booster circuit of a charge pump type using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A supply voltage inputted into this booster circuit varies in magnitude depending on a configuration of an electrical power system that supplies a supply voltage to the driver IC. Therefore, different input power voltages may be supplied to the same driver IC. For this reason, a technique has been desired by which a substrate area of the booster circuit is reduced, while achieving efficient boosting and outputting of a wide range of the input power voltages.
Such a booster circuit has been disclosed in Japanese Patent Application Laid Open No. 2005-304126, for example. FIG. 1 shows a configuration of a booster circuit 90 of such a booster circuit. The booster circuit 90 includes P channel MOS transistors P911 to P914, capacitors C1 to C4, P channel MOS transistors P921 and P923, N channel MOS transistors N921 and N923, and gate controllers 500, 600, 700, and 800.
The transistors P911 to P914 are connected in series between a supply voltage VDC1 and a boost voltage VDC3 to perform switching of a charge pump. The capacitors C1 to C4 are respectively connected to these transistors to maintain charge of the charge pump. The capacitor C1 is connected between a connection node of the transistors P911 and P912 and an output node of an inverter 921. The capacitor C2 is connected between a connection node of the transistors P912 and P913 and a voltage VSS. The capacitor C3 is connected between a connection node of the transistors P913 and P914 and an output node of an inverter 923. The capacitor C4 is connected between the supply voltage VDC3 and the supply voltage VSS.
The transistor P921 and the transistor N921 form the inverter 921. The transistor P923 and the transistor N923 form the inverter 923. The gate controllers 500, 600, 700, and 800 supply gate voltages VG1 to VG4 to the transistors P911 to P914, respectively.
The gate controller 500 includes inverters 521 to 523 and a level shifter 531. The gate controller 500 receives input of a boost clock signal VIN2, and applies the gate voltage VG1 to the transistor P911. The gate controller 600 includes inverters 621 to 623 and a level shifter 631. The gate controller 600 receives input of a boost clock signal VIN1, and applies the gate voltage VG2 to the transistor P912. The gate controller 700 includes inverters 721 to 723 and a level shifter 731. The gate controller 700 receives input of the boost clock signal VIN2, and applies the gate voltage VG3 to the transistor P913. The gate controller 800 includes inverters 821 to 823 and a level shifter 831. The gate controller 800 receives input of the boost clock signal VIN1, and applies the gate voltage VG4 to the transistor P914.
The boost clock signals VIN1 and VIN2 are signals whose high-level voltage is the supply voltage VDC1 and whose low-level voltage is the supply voltage VSS. The level shifters 531 and 631 each level-shift the high-level voltage of a corresponding one of these boost clock signals VIN1 and VIN2 from the voltage VDC1 to the voltage VDC2. Moreover, the level shifters 731 and 831 each level-shift the high-level voltage of a corresponding one of the boost clock signals VIN1 and VIN2 from the voltage VDC1 to the voltage VDC3.
The transistors P911 and P912, the inverter 921, and the capacitors C1 and C2 form first boost means, and the transistors P913 and P914, the inverter 923, and the capacitors C3 and C4 form second boost means. This booster circuit 90 performs charge pump operation when supplied with the boost clock signals VIN1 and VIN2. The first boost means boosts the supply voltage VDC1 to generate the supply voltage VDC2, and further, the second boost means boosts the supply voltage VDC2 to generate the supply voltage VDC3.
Here, for simplification of description, the supply voltage VSS as a reference voltage is as assumed to be 0 volt (grounding potential), and the supply voltage VDC1 is assumed to be V volts (for example, 2.8 volts). Moreover, description will be given assuming that the booster circuit 90 ideally operates, and that the supply voltage VDC2 is a voltage having been boosted to 2V volts (for example, 5.6 volts), and the supply voltage VDC3 is a voltage having been boosted to 3V volts (for example, 8.4 volts). Moreover, the transistors include a transistor having a breakdown voltage of approximately V (for example, 3 volts), a transistor having a breakdown voltage of approximately 2V (for example, 6 volts), and a transistor having a breakdown voltage of approximately 3V (for example, 9 volts), and these transistors will be referred to as a low breakdown voltage transistor, a middle breakdown voltage transistor, and a high breakdown voltage transistor, respectively.
FIG. 2 shows a configuration example of the level shifters 531, 631, 731, and 831 (generically referred to as n31). The level shifter n31 includes P channel MOS transistors P31 and P32, and N channel MOS transistors N31 and N32. Clock signals VINP and VINN are inputted into the gate of the N channel MOS transistor N31 and the gate of the N channel MOS transistor N32, respectively. The clock signal VINN is an inverted signal of the clock signal VINP.
The transistor P31 and the transistor N31 are connected in series between the supply voltage VDD and the supply voltage VSS. A connection node between the drains of the transistor P31 and the transistor N31 is connected to the gate of the transistor P32. The transistor P32 and the transistor N32 are connected in series between the supply voltage VDD and the supply voltage VSS. A connection node between the drains of the transistor P32 and the transistor N32 is connected to the gate of the transistor P31. An output signal VLSO whose high-level voltage is level-shifted to the voltage VDD is taken out from this node.
In the case of the level shifters 531 and 631, the voltage VDC2 (2V volts) is supplied as the supply voltage VDD. Therefore, in the level shifters 531 and 631, a voltage of 2V volts is applied between the gate and source or between the gate and drain of each transistor. The breakdown voltage of the low breakdown voltage transistor is inadequate when the breakdown voltage between the gate and source is approximately V volts. In other words, the middle breakdown voltage transistor having a breakdown voltage between the gate and source of approximately 2V volts needs to be used for each transistor of the level shifters 531 and 631.
In addition, in the case of the level shifters 731 and 831, the voltage VDC3, which is 3V volts, is supplied as the supply voltage VDD. Therefore, in the level shifters 731 and 831, a voltage of 3V volts is applied between the gate and source or between the gate and drain of each transistor. The breakdown voltage of the middle breakdown voltage transistor is inadequate when the breakdown voltage between the gate and source is approximately 2V volts. In other words, the high breakdown voltage transistor having a breakdown voltage between the gate and source of approximately 3V volts needs to be used for each transistor of the level shifters 731 and 831.
FIG. 3 shows a configuration of the inverters 521 to 523, 621 to 623, 721 to 723, and 821 to 823. Each inverter has a P channel MOS transistor P20 and an N channel MOS transistor N20 connected in series between supply voltages VDD1 and VDD0. An input signal INPUT is applied to the gate of the transistor P20 and the gate of the transistor N20, and an output signal OUTPUT is taken out from a connection node between the drains of the transistor P20 and the transistor N20. In the case of the inverters 521, 621, 721, and 821, the voltage VDC1 is supplied as the supply voltage VDD1, and the voltage VSS is supplied as the supply voltage VDD0. In the case of the inverters 522 to 523, 622 and 623, the voltage VDC2 is supplied as the supply voltage VDD1, and the voltage VSS is supplied as the supply voltage VDD0. In the case of the inverters 722, 723, 822, and 823, the voltage VDC3 is supplied as the supply voltage VDD1, and the voltage VDC1 is supplied as the supply voltage VDD0.
The inverters 521, 621, 721, and 821 are each supplied with the supply voltage VDC1 and the supply voltage VSS, and perform inversion operation to invert the clock signals VIN1 and VIN2. Therefore, the low breakdown voltage transistor can be used for the inverters 521, 621, 721, and 821. Moreover, the inverters 522, 523, 622, and 623 are each supplied with the supply voltage VDC2 and the supply voltage VSS, and function as an output buffer of the level shifters 531 and 631. Therefore, the middle breakdown voltage transistor needs to be used for the inverters 522, 523, 622, and 623. Further, the inverters 722, 723, 822, and 823 are each supplied with the supply voltage VDC3 and the supply voltage VDC1 and operate. The inverters 722 and 822 receive input of a signal, which changes between the supply voltage VDC3 and the supply voltage VSS, from the level shifters 731 and 831, respectively. The inverters 722 and 822 level-shift the low-level voltage of this input signal from the supply voltage VSS to the supply voltage VDC1. A voltage between the gate and source or between the gate and drain of the transistors included in the inverters 722 and 822 is 3V volts (for example, 8.4 volts). Therefore, the breakdown voltage of the middle breakdown voltage transistor is inadequate, and thus the high breakdown voltage transistor needs to be used. Moreover, the inverters 723 and 823 invert the signals which are outputted from the inverters 722 and 822, respectively, and which change between the voltage VDC1 and VDC3.
Next, operation of the booster circuit 90 will be described. Charge and discharge of the capacitors C1 and C3 are repeated by the switching operation of the transistors P911 to P914 and by the clock signal inversion operation of the inverters 921 and 923. Charge thereby moves to the capacitors C2 and C4, and the charge pump operation is performed. Specifically, the capacitor C1 is charged through the transistor P911, and the charge of the capacitor C1 moves to the capacitor C2 through the transistor P912, thereby to charge the capacitor C2. The voltage VDC2 of the capacitor C2 gradually rises, and reaches a voltage approximately twice (2V volts) the supply voltage VDC1 in the steady state. Moreover, the capacitor C3 is charged through the transistor P913, and the charge of the capacitor C3 moves to the capacitor C4 through the transistor P914, thereby to charge the capacitor C4. The voltage VDC3 of the capacitor C4 gradually rises, and reaches a voltage approximately three times (3V volts) the supply voltage VDC1 in the steady state.
FIGS. 4A to 4H show waveforms indicating voltage change of each part of the booster circuit 90 after reaching the steady state. The boost clock signals VIN1 (FIG. 4A) and VIN2 (FIG. 4B) are signals each having a phase opposite to the other. The high-level voltage is V volts and the low-level voltage is 0 volt.
The level shifters 531 and 631 level-shift the high level of the boost clock signals VIN2 and VIN1, respectively, so that signals whose high-level voltage is 2V volts and low-level voltage is 0 volt are obtained. These signals are each supplied as a gate voltage VG1 (FIG. 4F) of the transistor P911 and as a gate voltage VG2 (FIG. 4E) of the transistor P912. The transistors P911 and P912 are turned off when the gate voltage is at the high level, and turned on when the gate voltage is at the low level. Thereby, as shown in FIG. 4H, a voltage VP1 at one end of the capacitor C1 changes between 2V volts and V volts, and a voltage VM1 at the other end of the capacitor C1 changes between V volts and 0 volt.
The level shifters 731 and 831 level-shift the high level of the boost clock signals VIN2 and VIN1, respectively, to make the high-level voltage 3V volts. Moreover, each of the inverters 722 and 822 further level-shifts the low-level voltage of the thus-level-shifted signal to V volts. Thus, a gate voltage VG3 (FIG. 4D) applied to the gate of the transistor P913 and a gate voltage VG4 (FIG. 4C) applied to the gate of the transistor P914 are obtained. The transistors P913 and P914 are turned off when the gate voltage is at the high level, and turned on when the gate voltage is at the low level. Thereby, as shown in FIG. 4G, a voltage VP3 at one end of the capacitor C3 changes between 3V volts and 2V volts, and a voltage VM3 at the other end of the capacitor C3 changes between V volts and 0 volt.
Here, while the gate voltage VG3 of the transistor P913 and the gate voltage VG4 of the transistor P914 become 3V volts at the maximum, the minimum voltage becomes not 0 volt, but the voltage VDC1, i.e., V volts. A source voltage or drain voltage of the transistors P913 and P914 is 2V volts to 3V volts.
FIGS. 5A to 5F show voltage between nodes in each transistor. As shown in FIG. 5A, a voltage between the gate and source (drain) (VG2-VDC2, VG4-VDC3) of each of the transistors P912 and P914 changes between 0 volt and −2V volts. Moreover, as shown in FIG. 5B, a voltage between the gate and drain (source) (VG2-VP1, VG4-VP3) of each of the transistors P912 and P914 changes between V volts and −2V volts. Further, as shown in FIG. 5C, a voltage between the source and drain of each of the transistors P912 and P914 (VDC2-VP1, VDC3-VP3) changes between V volts and 0 volt.
Moreover, as shown in FIG. 5D, a voltage between the gate and source (drain) (VG1-VP1, VG3-VP3) of each of the transistors P911 and P913 changes between V volts and −2V volts. As shown in FIG. 5E, a voltage between the gate and drain (source) (VG1-VDC1, VG3-VDC2) of each of the transistors P911 and P913 changes between V volts and −V volts. Further, as shown in FIG. 5F, a voltage between the source and drain of each of the transistors P911 and P913 (VP1-VDC1, VP3-VDC2) changes between V volts and 0 volt.